The mechanisms of parasitic effects in combined memristor-diode arrays of logic and memory matrices within a neuroprocessor are described. To assess the impact of parasitic effects on the output signal waveform and cell states, circuit models of the matrices are developed by incorporating parasitic elements, known memristor models, and Zener diode models into LTspice. Numerical simulations demonstrate that in both matrices, the primary contribution to signal propagation delays comes from RC circuits formed by the load resistance, parasitic cell capacitance, and substrate capacitance. The nonlinear increase in signal propagation delay is shown to depend on the crossbar array dimensionality and memristor size. Compensation methods for parasitic effects are proposed, including modifications to the encoding scheme and reduction of the memristor dimensions to 100 nm.